1. Field of the Invention
The present invention relates to a decoding technique, and particularly to a decoding apparatus and a decoding method for decoding data subjected to LDPC encoding.
2. Description of the Related Art
In recent years, LDPC (Low Density Parity Check Code) has been attracting attention as an error correction code having a strong error correction capability even if a low S/N channel is employed. Thus, LDPC has been applied in many fields. With such LDPC, the data is encoded on the transmitter side using an encoding matrix generated based on a low density check matrix. Here, the “low density check matrix” represents a matrix having elements which are either 1 or 0, wherein the number of “1” elements is small. On the other hand, on the receiver side, the data decoding and parity check are performed based on the check matrix. In particular, by means of iterative decoding such as a BP (Belief Propagation) method or the like, such an arrangement provides improved decoding performance.
With such a decoding method, check node processing, which is decoding using a check matrix in the row direction, and variable node processing, which is decoding using the check matrix in the column direction, are iteratively executed. Known examples of the check node processing include sum-product decoding using a Gallager function or otherwise a hyperbolic function. With sum-product decoding, a channel value, which can be calculated based on the variance of the transmission channel noise, is used as a prior value.
Furthermore, min-sum decoding is known, which is obtained by simplifying the sum-product decoding. Min-sum decoding allows the check node processing to be executed without involving complicated functions, i.e., requires only simple functions such as a comparison operation, a sum operation, and the like to execute the check node processing. Furthermore, min-sum decoding does not require a transmission channel value. Thus, min-sum decoding is widely employed in order to provide high-speed processing in a simple manner. In order to reduce the circuit scale for min-sum decoding, a technique has been provided in which the minimum value and the second minimum value are extracted from the prior value ratios for each row of the check matrix.
The processing for deriving the minimum value of the prior value ratio for each row of the check matrix requires only a very simple circuit configuration. However, in order to derive the second minimum value, such an arrangement requires an operation in which the second minimum value is again detected after the minimum value is derived, or otherwise requires two memory units and a memory swapping operation, leading to a problem of a complicated circuit configuration. Thus, there is a demand for a technique for reducing the amount of calculation required for min-sum decoding.